1. Field of the Invention
The present invention relates to a method of fabricating semiconductor. More particularly, the present invention relates to a method of fabricating a nitrogen-containing gate dielectric layer and a semiconductor device.
2. Description of the Related Art
With the progressive drop in the dimension of the metal-oxide-semiconductor (MOS) transistor s, more stringent quality requirements are set up for the gate dielectric layer. When the dimension of a MOS transistor drops to a value smaller than 0.1 μm, the thickness of a gate dielectric layer fabricated using silicon oxide layer must also be reduced to a value below 20 Å. As the thickness of the gate dielectric layer grows thinner and thinner, electrons can easily tunnel through the layer to produce a leakage current if there is any defect in the gate dielectric layer.
Therefore, if the gate dielectric layer is fabricated using silicon oxide material, then a nitridation process is often carried out to adjust the properties of the gate dielectric layer and reduce the leakage current and other electrical problems in the device. In the conventional technique, nitridation is performed through implanting nitrogen into the gate dielectric layer in a plasma process. However, this method frequently damages the internal structure of the gate dielectric and leads to quality problems. Moreover, the cost for carrying out a plasma nitridation process is high.
Conventionally, there is also an alternative thermal process for nitriding of the gate dielectric layer. However, this method will form a deeper nitrogen concentration distribution curve. In other words, the interface between the nitrogen and the silicon oxide is very close to the silicon oxide/substrate interface. Thus, it can easily lead to a flatband voltage variation and an increase in the trapped charges inside the gate dielectric layer, a major cause of electrical problems. In addition, it may affect the threshold voltage, the difference in work function between the substrate and the gate and the reliability of the device and so lead to negative bias and negative bias temperature instability (NBTI) problem resulting in a drop in the performance of the semiconductor device. Furthermore, the convention method permits a reaction chamber to process only a single wafer at a time, which may result in a bottleneck in production.